RISC is an acronym for reduced instruction set computer. Despite the name, RISC does not actually refer to an entire computer, but rather to a type of CPU architecture. These central processing units are the heart of the computer, but they are not the entire machine. RISC-CPUs, specifically, are built in order to keep the instructions that the microprocessor has to go through to a minimum.
Technipages Explains RISC
Since CPUs can only effectively process one instruction at a time, and not several at once, so effectively structuring, sorting and ordering them is a priority in engineering the processors. The idea of the RISC architecture was to eliminate everything that can possibly be removed while emphasizing on optimised instructions for faster execution. This was, however, not entirely without flaws – RISC had very little success at a desktop computer level, where competing x86 architecture remained the most popular type of CPU. Despite this, RISC did find some success on mobile and console platforms.
The alternative to RISC CPUs is CISC architecture – complex instruction set computer architecture, to be precise. These CISC builds are what Intel uses for their own CPUs – and the main competitor of RISC builds. IBM used it for some of their processors – among other things, these featured in the Wii, PlayStation 3, GameCube and Xbox 360 among other things. Both types of architecture have their advantages and disadvantages, but the main difference is speed versus usability – while RISC is faster, it’s much easier for developers to program specifically for CISC processors.
Common Uses of RISC
- RISC processors are effectively faster than their counterparts, yet could not overtake the market-dominating CISC technology.
- While RISC processors found success in some IBM products, competitors went with alternatives like MISC or CISC.
- The pipeline architecture of RISC processors means that they can process instructions in ordered batches, though still one at a time.
Common Misuses of RISC
- RISC processors are the industry standard of CPU builds.